The present invention relates to amplifier devices, and more particularly, to a low noise amplifier device (LNA) with gain switching. The invention applies especially, but not exclusively, for use in a receiver front end that receives radio frequency signals, such as those intended for mobile telephony circuits.
Low noise input amplifiers of a radio frequency receiving system generally make use of gain switching for reducing the dynamic range constraints imposed on the first frequency conversion stage. Such an amplifier generally operates according to two modes, a high gain mode and a low gain mode.
In the high gain mode, the gain of the amplifier, in terms of power, has to be sufficient, and is typically greater than 15 dB. However, in the presence of signals having stronger power, the gain of the amplifier is cut and the low gain operating mode is entered, in which the gain is typically on the order of xe2x88x925 dB.
To keep the matching of the amplifier constant in the two gain modes, in terms of power, a structure is generally used of the type comprising amplification means. The amplification means generally includes a bipolar transistor which constitutes the heart of the amplifier, and a configurable load circuit. The configurable load circuit includes an inductive element and two resistive elements, and is capable of exhibiting two different configurations respectively having two different impedance values.
A controllable switching means is connected between the amplification means and the load circuit to select one of the two configurations of the load circuit. This switching means is generally formed by two bipolar transistors, one of which is connected to the common terminal of the two resistive elements and the other of which is connected to the common terminal between one of the resistive elements and the inductive element.
The selection between the high gain mode and the low gain mode takes place by turning off one of the two transistors of the switching means while the other one is kept turned on. In the high gain mode, the power gain is a function (to a first approximation) of the bias current of the transistor of the amplification means, of the degeneracy inductor connected to the emitter of the transistor, and of the losses of the matching networks present at the input and at the output of the amplifier.
However, the power gain is limited by the value of the resistor connected between the two switching transistors, and therefore, the value has to be sufficiently high. In the low gain mode, the power gain is fixed by the ratio of the two resistors which has to be on the order of 1/10 to obtain an attenuation of xe2x88x925 dB, which corresponds to about 20 dB less than in the high gain mode.
In wireless communications systems of the type operating according to the wideband CDMA (WCDMA) standard, which is well known to the person skilled in the art, a relatively high gain is specified to be obtained in the high gain mode, and is typically a gain on the order of 16 dB. However, with regards to the resistance values used, the maximum gain available for the amplifier reaches this value only with difficulty.
Furthermore, in the low gain mode, the value of the other resistor, which has to be ten times less than that of the abovementioned resistor, is at the origin of an internal overvoltage on the collector of one of the two switching transistors. The compression point is therefore limited by the dynamic range of the signal while the amplifier is operating in an attenuator mode. In conclusion, in conventional amplification devices, the choice of the values of the resistive elements of the load circuit results from a compromise between the gain in the high gain mode and the compression point in the low gain mode.
In view of the foregoing background, an object of the invention is to optimize the output dynamic range in the low gain mode while maintaining a high gain in the high gain mode.
This and other objects, advantages and features according to the invention are provided by an amplifier device with gain switching, and comprises amplification means and a configurable load circuit. The configurable load circuit includes an inductive element that is capable of exhibiting two different configurations having two different impedance values. Controllable switching means is connected between the amplification means and the load circuit to select one of the two configurations.
According to one general characteristic of the invention, the load circuit includes two insulated-gate field effect load transistors connected in series and operate in the triode mode. The inductive element is connected in parallel with the pair of load transistors between a power supply terminal and the switching circuit.
The operation of the load transistors in the triode mode, that is, control via the gate voltage of the flow of the current between the source and the drain, makes it possible to turn these load transistors off or on depending on the gain desired. More precisely, when the load transistors are turned off, they operate like a capacitive network leading to maximum gain, while, when they are turned on, they operate like resistors making it possible to lower the gain. In the high gain mode, that is, when the transistors are turned off, they do not introduce any resistive loss.
According to one embodiment of the invention, the two load transistors are both controllable on the gate by the same control signal (gate voltage). A first terminal of the inductive element is connected to the power supply terminal, and the second terminal of the inductive element is connected to a first switching input of the switching means. The common terminal of the two load transistors is connected to a second switching input of the switching means. The device also includes selection means for delivering a selection signal to the switching means for selecting the configuration, and to deliver the control signal in such a way as to turn the two transistors off or on depending on the configuration selected.
According to one embodiment of the invention, the switching means includes a first switching transistor connected between the amplification means and the first switching input, and a second switching transistor connected between the amplification means and the second switching input. In a first configuration of the load circuit (corresponding to the high gain mode, for example), the load transistors are turned off, the first switching transistor is turned on and the second switching transistor is turned off.
In a second configuration of the load circuit (corresponding to the low gain mode, for example), the load transistors are turned on, the first switching transistor is turned off and the second switching transistor is turned on. In the low gain mode, that is, in the second configuration, the load transistor connected between the two switching inputs has to exhibit the highest resistance.
As a result, this load transistor features a channel width which is less than that of the other load transistor, which has to exhibit a much lower resistance. This is particularly advantageous, since the smaller transistor which is connected between the collector of the second switching transistor and the inductive element exhibits a low value of stray capacitance which is much easier to handle than a capacitance having a larger value.
Although it would be possible to use NMOS transistors as load transistors, load transistors of the PMOS type will preferably be used, which makes it possible to control them on their gate via a positive control voltage. Furthermore, to avoid the PMOS transistors from becoming turned on accidentally in the high gain mode in the presence of a strong output signal, a value at least equal to that of the power supply voltage increased by the threshold voltage of the drain-substrate diode of a load transistor will advantageously be chosen for the control voltage.
Another aspect of the invention is directed to a radio frequency receiver, for example, a cellular mobile telephone incorporating an amplifier device according to the invention.